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Preliminary
FM22L16
4Mbit FRAM Memory Features
4Mbit Ferroelectric Nonvolatile RAM * Organized as 256Kx16 * Configurable as 512Kx8 Using /UB, /LB * 1014 Read/Write Cycles * NoDelayTM Writes * Page Mode Operation to 40MHz * Advanced High-Reliability Ferroelectric Process SRAM Compatible * JEDEC 256Kx16 SRAM Pinout * 55 ns Access Time, 110 ns Cycle Time Advanced Features * Low VDD Monitor Protects Memory against Inadvertent Writes * Software Programmable Block Write Protect Superior to Battery-backed SRAM Modules * No Battery Concerns * Monolithic Reliability * True Surface Mount Solution, No Rework Steps * Superior for Moisture, Shock, and Vibration Low Power Operation * 2.7V - 3.6V Power Supply * Low Current Mode (5A) using ZZ pin * 18 mA Active Current Industry Standard Configuration * Industrial Temperature -40 C to +85 C * 44-pin "Green"/RoHS TSOP-II package
Description
The FM22L16 is a 256Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or FRAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and unlimited write endurance make FRAM superior to other types of memory. In-system operation of the FM22L16 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by /CE or simply by changing the address. The FRAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM22L16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. The FM22L16 includes a low voltage monitor that blocks access to the memory array when VDD drops below a critical threshold. The memory is protected against an inadvertent access and data corruption under this condition. The device also features software-controlled write protection. The memory
array is divided into 8 uniform blocks, each of which can be individually write protected. The device is available in a 400 mil 44-pin TSOP-II surface mount package. Device specifications are guaranteed over industrial temperature range -40C to +85C. Pin Configuration
A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 /ZZ A8 A9 A10 A11 A12
Ordering Information FM22L16-55-TG 55 ns access, 44-pin "Green"/RoHS TSOP-II
This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.0 Mar. 2007
Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 15
FM22L16
Address Latch & Write Protect
Block & Row Decoder
Figure 1. Block Diagram Pin Description Pin Name Type A(17:0) Input
/CE
Input
/WE
Input
/OE /ZZ
Input Input
DQ(15:0) /UB /LB VDD VSS
Rev. 1.0 Mar. 2007
I/O Input Input Supply Supply
Pin Description Address inputs: The 18 address lines select one of 262,144 words in the FRAM array. The lowest two address lines A(1:0) may be used for page mode read and write operations. Chip Enable input: The device is selected and a new memory access begins when /CE is low and /ZZ is high. The entire address is latched internally on the falling edge of /CE. Subsequent changes to the A(1:0) address inputs allow page mode operation when /CE is low. Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM22L16 to write the data on the DQ bus to the FRAM array. The falling edge of /WE latches a new column address for fast page mode write cycles. Output Enable: When /OE is low, the FM22L16 drives the data bus when valid read data is available. De-asserting /OE high tri-states the DQ pins. Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest current condition. Since this input is logically AND'd with /CE, /ZZ must be high for normal read/write operation. Data: 16-bit bi-directional data bus for accessing the FRAM array. Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z if /UB is high. Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z if /LB is high. Supply Voltage: 3.3V Ground
...
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FM22L16 Functional Truth Table 1,2 /CE /WE A(17:2) X X X H X X H V L H No Change L H Change L V L V L No Change X X
Notes: 1) 2) 3) 4) H=Logic High, L=Logic Low, V=Valid Data, X=Don't Care. /WE-controlled write cycle begins as a Read cycle. Addresses A(1:0) must remain stable for at least 10 ns during page mode operation. For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
A(1:0) X X V Change V V V V X
/ZZ L H H H H H H H H
Operation Sleep Mode Standby/Idle Read Page Mode Read Random Read /CE-Controlled Write /WE-Controlled Write 2 Page Mode Write 3 Starts Precharge
Byte Select Truth Table /OE /LB /UB H X X X H H L H L L H L L X H L L H L L
Operation Read; Outputs Disabled Read; DQ(7:0) Hi-Z Read; DQ(15:8) Hi-Z Read Write; Mask DQ(7:0) Write; Mask DQ(15:8) Write
Simplified Sleep/Standby State Diagram
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FM22L16
Overview
The FM22L16 is a wordwide FRAM memory logically organized as 262,144 x 16 and accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page requires that either /CE transitions low or the upper address A(17:2) changes. and /WE-controlled write cycles. In both cases, the address A(17:2) is latched on the falling edge of /CE. In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the device begins the memory cycle as a write. The FM22L16 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when /CE is de-asserted high. In a /WE-controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE-controlled write timing cases are shown in the Electrical Specifications section. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever comes first. A valid write operation requires the user to meet the access time specification prior to de-asserting /WE or /CE. Data setup time indicates the interval during which data cannot change prior to the end of the write access (rising edge of /WE or /CE). Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FRAM array is organized as 8 blocks each having 8192 rows. Each row has 4 column address locations. Address inputs A(1:0) define the column address to be accessed. An access can start on any column address, and other column locations may be accessed without the need to toggle the /CE pin. For fast access reads, once the first data byte is driven onto the bus, the column address inputs A (1:0) may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While /CE is low, a subsequent write pulse along with a new column address provides a page mode write access.
Memory Operation
Users access 262,144 memory locations, each with 16 data bits through a parallel interface. The FRAM array is organized as 8 blocks each having 8192 rows. Each row has 4 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE, subsequent column locations may be accessed without the need to toggle /CE. When /CE is deasserted high, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to FRAM called NoDelayTM writes. Read Operation A read operation begins on the falling edge of /CE. The falling edge of /CE causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latched and the access completed, a new access to a random location (different row) may begin while /CE is still low. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM22L16's /CE-initiated access time is faster than the address cycle time. The FM22L16 will drive the data bus when /OE and at least one of the byte enables (/UB, /LB) is asserted low. The upper data byte is driven when /UB is low, and the lower data byte is driven when /LB is low. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is deasserted high, the data bus will remain in a high-Z state. Write Operation Writes occur in the FM22L16 in the same time interval as reads. The FM22L16 supports both /CERev. 1.0 Mar. 2007
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FM22L16 Precharge Operation The precharge operation is an internal condition in which the state of the memory is being prepared for a new access. Precharge is user-initiated by driving the /CE signal high. It must remain high for at least the minimum precharge time tPC. after the correct six addresses will not be entered into memory. The protection data byte consists of 8-bits, each associated with the write protect state of a sector. The data byte must be driven to the lower 8-bits of the data bus, DQ (7:0). Setting a bit to 1 write protects the corresponding sector; a 0 enables writes for that sector. The following table shows the write-protect sectors with the corresponding bit that controls the write-protect setting. Write Protect Sectors - 32K x16 blocks Sector 7 3FFFFh - 38000h Sector 6 37FFFh - 30000h Sector 5 2FFFFh - 28000h Sector 4 27FFFh - 20000h Sector 3 1FFFFh - 18000h Sector 2 17FFFh - 10000h Sector 1 0FFFFh - 08000h Sector 0 07FFFh - 00000h The write-protect read address sequence follows: 1. 24555h * 2. 3AAAAh 3. 02333h 4. 1CCCCh 5. 000FFh 6. 3EF00h 7. 3AAAAh 8. 1CCCCh 9. 0FF00h 10. 00000h * If /CE is low entering the sequence, then an address of 00000h must precede 24555h. The address sequence provides a very secure way of modifying the protection. The write-protect sequence has a 1 in 3 x 1032 chance of randomly accessing exactly the 1st six addresses. The odds are further reduced by requiring three more write cycles, one that requires an exact inversion of the data byte. A flow chart of the entire write protect operation is shown in Figure 2. The write-protect settings are nonvolatile. The factory default: all blocks are unprotected.
Software Write Protection
The 256Kx16 address space is divided into 8 sectors (blocks) of 32Kx16 each. Each sector can be individually software write-protected and the settings are nonvolatile. A unique address and command sequence invokes the write protection mode. To modify write protection, the system host must issue six read commands, three write commands, and a final read command. The specific sequence of read addresses must be provided in order to access to the write protect mode. Following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. For confirmation, the system must then write the complement of the protection byte immediately following the protection byte. Any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write protection unchanged. The write protect state machine monitors all addresses, taking no action until this particular read/write sequence occurs. During the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven onto the data bus. Any address that occurs out of sequence will cause the software protection state machine to start over. After the address sequence is completed, the next operation must be a write cycle. The data byte contains the write-protect settings. This value will not be written to the memory array, so the address is a don't-care. Rather it will be held pending the next cycle, which must be a write of the data complement to the protection settings. If the complement is correct, the write protect settings will be adjusted. If not, the process is aborted and the address sequence starts over. The data value written
Rev. 1.0 Mar. 2007
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FM22L16
Figure 2. Write-Protect State Machine For example, the following sequence write-protects addresses from 18000h to 27FFFh (sectors 3 & 4): Read Read Read Read Read Read Write Write Write Read
Rev. 1.0 Mar. 2007
Address 24555h 3AAAAh 02333h 1CCCCh 000FFh 3EF00h 3AAAAh 1CCCCh 0FF00h 00000h
Data 18h E7h -
; ; ; ;
bits 3 & 4 = 1 complement of 18h Data is don't care return to Normal Operation
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FM22L16
Software Write Protect Timing
SRAM Drop-In Replacement
The FM22L16 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely. While /CE is low, the device automatically detects address changes and a new access is begun. This functionality allows /CE to be grounded as you might with an SRAM. It also allows page mode operation at speeds up to 40MHz. Note that if /CE is tied to ground, the user must be sure /WE is not low at powerup or powerdown events. If /CE and /WE are both low during power cycles, data corruption will occur. For applications that require the lowest power consumption, the /CE signal should be active only during memory accesses. The FM22L16 draws IDD supply current while /CE is low, even if addresses and control signals are static. While /CE is high, the device draws no more than the maximum standby current ISB. The FM22L16 is backward compatible with the 1Mbit FM20L08 and 256Kbit FM18L08 devices.
That is, operating the FM22L16 with /CE toggling low on every address is perfectly acceptable. The /UB and /LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 512Kx8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A(18) may be available from the system processor.
Figure 3. FM22L16 Wired as 512Kx8
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FM22L16
Electrical Specifications
Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS TSTG TLEAD Storage Temperature Lead Temperature (Soldering, 10 seconds) Ratings -1.0V to +4.5V -1.0V to +4.5V and VIN < VDD+1V -55C to +125C 300 C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 2.7 3.3 3.6 V IDD1 VDD Supply Current 18 mA 1 IDD2 VDD Supply Current - CMOS 1.5 mA 2 ISB2 Standby Current - CMOS 150 3 A IZZ Sleep Mode Current 5 4 A ILI Input Leakage Current 1 A ILO Output Leakage Current 1 A VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.6 V VOH1 Output High Voltage (IOH = -1.0 mA) 2.4 V VOH2 Output High Voltage (IOH = -100 A) VDD-0.2 V VOL1 Output Low Voltage (IOL = 2.1 mA) 0.4 V VOL2 Output Low Voltage (IOL = 100 A) 0.2 V Notes 1. VDD = 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded. 2. VDD = 3.6V, /CE at VSS, All other pins are static and at CMOS levels (0.2V or VDD-0.2V), /ZZ is high. 3. VDD = 3.6V, /CE at VDD, All other pins are static and at CMOS levels (0.2V or VDD-0.2V), /ZZ is high. 4. VDD = 3.6V, /ZZ is low, all other inputs at CMOS levels (0.2V or VDD-0.2V).
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FM22L16 Read Cycle AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) -55 Symbol Parameter Min Max Units Notes tRC Read Cycle Time 110 ns tCE Chip Enable Access Time 55 ns tAA Address Access Time 110 ns tOH Output Hold Time 20 ns tAAP Page Mode Address Access Time 35 ns tOHP Page Mode Output Hold Time 5 ns tCA Chip Enable Active Time 55 ns tPC Precharge Time 55 ns tBA /UB, /LB Access Time 30 ns tAS Address Setup Time (to /CE low) 0 ns tAH Address Hold Time (/CE-controlled) 55 ns tOE Output Enable Access Time 10 ns tHZ Chip Enable to Output High-Z 10 ns 1 tOHZ Output Enable High to Output High-Z 10 ns 1 tBHZ /UB, /LB High to Output High-Z 10 ns 1 Write Cycle AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) -55 Symbol Parameter Min Max Units Notes tWC Write Cycle Time 110 ns tCA Chip Enable Active Time 55 ns tCW Chip Enable to Write Enable High 55 ns tPC Precharge Time 55 ns tBHZ /UB, /LB High to Output High-Z 5 ns tPWC Page Mode Write Enable Cycle Time 35 ns tWP Write Enable Pulse Width 16 ns tAS Address Setup Time (to /CE low) 0 ns tASP Page Mode Address Setup Time (to /WE low) 8 ns tAHP Page Mode Address Hold Time (to /WE low) 15 ns tWLC Write Enable Low to /CE High 25 ns tWLA Write Enable Low to A(17:2) Change 25 ns tAWH A(17:2) Change to Write Enable High 110 ns tDS Data Input Setup Time 14 ns tDH Data Input Hold Time 0 ns tWZ Write Enable Low to Output High Z 10 ns 1 tWX Write Enable High to Output Driven 10 ns 1 tWS Write Enable to /CE Low Setup Time 0 ns 2 tWH Write Enable to /CE High Hold Time 0 ns 2
Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. The parameters tWS and tWH are not tested.
Capacitance Symbol CI/O CIN CZZ
(TA = 25 C , f=1 MHz, VDD = 3.3V)
Parameter Input/Output Capacitance (DQ) Input Capacitance Input Capacitance of /ZZ pin
Max 8 6 8
Units pF pF pF
Notes
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FM22L16 Power Cycle Timing (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Max tPU Power-Up to First Access Time (after VDD min) 450 tPD Power-Down to Last Access Time (prior to VTP) 0 tVR VDD Rise Time 50 tVF VDD Fall Time 100 tZZEN Sleep Mode Enter Time (/ZZ low to /CE don't care) 0 tZZEX Sleep Mode Exit Time (/ZZ high to 1st access after wakeup) 450 -
Units s s s/V s/V s s
Notes
1,2 1,2
Notes 1 Slope measured at any point on VDD waveform. 2 Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than 100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V) Parameter Data Retention
Min 10
Units Years
Notes
AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Output Load Capacitance
0 to 3V 3 ns 1.5V 30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
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FM22L16 Page Mode Read Cycle Timing
* Although sequential column addressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled, /OE low)
Write Cycle Timing 2 (/CE-Controlled)
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FM22L16 Write Cycle Timing 3 (/CE low)
Page Mode Write Cycle Timing
* Although sequential column addressing is shown, it is not required.
Sleep Mode Enter/Exit Timing
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FM22L16 Power Cycle Timing
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FM22L16
Mechanical Drawing
44-pin TSOP-II (Complies with JEDEC Standard MS-024g Var. AC)
E1
E
Pin 1
D
L A A2 C
e
b
A1
0.10 mm
Symbol A A1 A2 b C D E E1 e L
Min. 0.05 0.95 0.30 0.12 11.56 0.40 0
Nom. 1.00 18.41 BASIC 11.76 10.16 0.80 BSC 0.50 -
Max. 1.20 0.15 1.05 0.45 0.20 11.96 0.60 8
Note: All dimensions in millimeters.
Rev. 1.0 Mar. 2007
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FM22L16
Revision History
Revision 1.0 Date 3/9/07 Summary Initial release.
Rev. 1.0 Mar. 2007
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